Machine Learnin… (2021-01-10T00:00:00.000000Z)

TL;DR

A comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy is presented.

Abstract

With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interest in incorporating ML to solve EDA tasks. In this article, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

Authors

Guyue Huang

1 papers

Jingbo Hu

1 papers

Yifan He

1 papers

TL;DR

Abstract

Authors

References186 items

Global Placement with Deep Learning-Enabled Explicit Routability Optimization

Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks

Hotspot Detection via Attention-based Deep Layout Metric Learning

Empyrean ALPS-GT: GPU-accelerated Analog Circuit Simulation

Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk)

GridNet: Fast Data-Driven EM-Induced IR Drop Prediction and Localized Fixing for On-Chip Power Grid Networks*

Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization

PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning

A Customized Graph Neural Network Model for Guiding Analog IC Placement

VLSI Placement Parameter Optimization using Deep Reinforcement Learning

A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CAD

Routing-Free Crosstalk Prediction

Learn to Floorplan through Acquisition of Effective Local Search Heuristics

A general approach for identifying hierarchical symmetry constraints for analog circuit layout

Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble

DAMO: Deep Agile Mask Optimization for Full Chip Scale

TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs

Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration

MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design

ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis

Exploring a Machine Learning Approach to Performance Driven Analog IC Placement

GRANNITE: Graph Neural Network Inference for Transferable Power Estimation

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning

Chip Placement with Deep Reinforcement Learning

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning

GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits

Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks

AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs

PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques

FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning

S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity

VLSI Mask Optimization: From Shallow To Deep Learning

PyTorch: An Imperative Style, High-Performance Deep Learning Library

DRiLLS: Deep Reinforcement Learning for Logic Synthesis

Electric Analog Circuit Design with Hypernetworks And A Differential Simulator

LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance

GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization

IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop

Improving Test Chip Design Efficiency via Machine Learning

Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection

RePlAce: Advancing Solution Quality and Routability Validation in Global Placement

Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design

BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks

LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks

Faster Region-based Hotspot Detection

DREAMPIace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement

A Learning-Based Recommender System for Autotuning Design FIows of Industrial High-Performance Processors

High Performance Graph ConvolutionaI Networks with Applications in Testability Analysis

WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout

PRIMAL: Power Inference using Machine Learning

Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism

Late Breaking Results: An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis

Circuit-GNN: Graph Neural Networks for Distributed Circuit Design

Guiding High-Performance SAT Solvers with Unsat-Core Predictions

NeuroCore: Guiding High-Performance SAT Solvers with Unsat-Core Predictions

Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning

Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis

XPPE: cross-platform performance estimation of hardware accelerators using machine learning

SRAF Insertion via Supervised Dictionary Learning

Detecting Multi-Layer Layout Hotspots with Adaptive Squish Patterns

Learning-Based Prediction of Package Power Delivery Network Quality

Semi-Supervised Hotspot Detection with Self-Paced Multi-Task Learning

Learning to Design Circuits

Machine Learning for Design Space Exploration and Optimization of Manycore Systems

HLSPredict: Cross Platform Performance Prediction for FPGA High-Level Synthesis

RouteNet: Routability prediction for Mixed-Size Designs Using Convolutional Neural Network

Inference of Suitable for Required Specification Analog Circuit Topology using Deep Learning

Learning To Solve Circuit-SAT: An Unsupervised Differentiable Approach

Learning Heuristics for Automated Reasoning through Deep Reinforcement Learning

Machine-Learning Based Congestion Estimation for Modern FPGAs

Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach

UNet++: A Nested U-Net Architecture for Medical Image Segmentation