1
Ps and Qs: Quantization-Aware Pruning for Efficient Low Latency Neural Network Inference
2
Fast convolutional neural networks on FPGAs with hls4ml
3
Design of a reconfigurable autoencoder algorithm for detector front-end ASICs
4
Mix and Match: A Novel FPGA-Centric Deep Neural Network Quantization Framework
5
FPGAs-as-a-Service Toolkit (FaaST)
6
Distance-Weighted Graph Neural Networks on FPGAs for Real-Time Particle Reconstruction in High Energy Physics
7
Ultra Low-latency, Low-area Inference Accelerators using Heterogeneous Deep Quantization with QKeras and hls4ml
8
Automatic deep heterogeneous quantization of Deep Neural Networks for ultra low-area, low-latency inference on the edge at particle colliders
9
Model Compression and Hardware Acceleration for Neural Networks: A Comprehensive Survey
10
Compressing deep neural networks on FPGAs to binary and ternary precision with hls4ml
11
Benchmarking TinyML Systems: Challenges and Direction
12
What is the State of Neural Network Pruning?
13
Comparing Rewinding and Fine-tuning in Neural Network Pruning
14
A comprehensive survey on model compression and acceleration
15
Fast inference of Boosted Decision Trees in FPGAs for particle physics
16
HLS4ML LHC Jet dataset (150 particles)
17
A flexible FPGA accelerator for convolutional neural networks
19
Are We There Yet? A Study on the State of High-Level Synthesis
20
HAWQ: Hessian AWare Quantization of Neural Networks With Mixed-Precision
21
FixyNN: Efficient Hardware for Mobile Computer Vision via Transfer Learning
22
FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review
23
Quantized Guided Pruning for Efficient Hardware Implementations of Convolutional Neural Networks
24
HAQ: Hardware-Aware Automated Quantization
26
INVITED: A Modular Digital VLSI Flow for High-Productivity SoC Design
27
UNIQ: Uniform Noise Injection for the Quantization of Neural Networks
28
Fast inference of deep neural networks in FPGAs for particle physics
29
Toolflows for Mapping Convolutional Neural Networks on FPGAs
30
Accelerating CNN inference on FPGAs: A Survey
31
The Lottery Ticket Hypothesis: Training Pruned Neural Networks
32
Learning Sparse Neural Networks through L0 Regularization
33
fpgaConvNet: A Toolflow for Mapping Diverse Convolutional Neural Networks on Embedded FPGAs
34
Minimum energy quantized neural networks
35
A Survey of Model Compression and Acceleration for Deep Neural Networks
36
The importance of calorimetry for highly-boosted jet substructure
37
Latency-driven design for FPGA-based convolutional neural networks
38
Snowflake: An efficient hardware accelerator for convolutional neural networks
39
Where's the Bear? - Automating Wildlife Image Processing Using IoT and Edge Cloud Systems
40
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates
41
FarmBeats: An IoT Platform for Data-Driven Agriculture
42
fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only)
43
FINN: A Framework for Fast, Scalable Binarized Neural Network Inference
44
From high-level deep neural models to FPGAs
45
A Survey and Evaluation of FPGA High-Level Synthesis Tools
46
Caffeinated FPGAs: FPGA framework For Convolutional Neural Networks
47
Quantized Neural Networks: Training Neural Networks with Low Precision Weights and Activations
48
Deep neural networks are robust to weight binarization and other non-linear distortions
49
Ternary Weight Networks
50
fpgaConvNet: A Framework for Mapping Convolutional Neural Networks on FPGAs
51
XNOR-Net: ImageNet Classification Using Binary Convolutional Neural Networks
52
Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array
53
Quantized Convolutional Neural Networks for Mobile Devices
54
BinaryConnect: Training Deep Neural Networks with binary weights during propagations
55
Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding
56
Learning both Weights and Connections for Efficient Neural Network
57
Batch Normalization: Accelerating Deep Network Training by Reducing Internal Covariate Shift
58
Deep Learning with Limited Numerical Precision
59
Compressing Deep Convolutional Networks using Vector Quantization
60
Caffe: Convolutional Architecture for Fast Feature Embedding
61
1.1 Computing's energy problem (and what we can do about it)
62
Deep Sparse Rectifier Neural Networks
63
Rectified Linear Units Improve Restricted Boltzmann Machines
64
Measuring the Gap Between FPGAs and ASICs
65
Feature selection, L1 vs. L2 regularization, and rotational invariance
66
fastmachinelearning/hls4ml: bartsia (v0.5.0)
67
Xilinx/finn. https://github.com/Xilinx/finn
68
Towards Automatic High-Level Code Deployment on Reconfigurable Platforms: A Survey of High-Level Synthesis Tools and Toolchains
69
NeckSense: A Multi-Sensor Necklace for Detecting Eating Activities in Free-Living Conditions
71
High-Level Synthesis to On-chip Implementation of a Reconfigurable AI Accelerator for Front-end Data Analysis at the HL-LHC
72
A Survey of FPGA-Based Neural Network Inference Accelerator
73
ARM-software/DeepFreeze
74
Learningsparseneuralnetworksthrough 𝐿 0 regularization In 6th International Conference on Learning Representations
75
7 Series DSP48E1 slice user guide
76
Binarized Neural Networks
77
TensorFlow: Large-Scale Machine Learning on Heterogeneous Systems. https://www.tensorflow.org/ Software available from tensorflow.org
78
Torch7: A Matlab-like Environment for Machine Learning
79
Improving the speed of neural networks on CPUs
80
MNIST handwritten digit database. http://yann.lecun.com/ exdb/mnist
82
Learning Devices TinyML Research Symposium’21
83
Catapult High-Level Synthesis -Verification
